1. Field of Invention
This invention relates to a graphic control system for a digital color raster scan display and more particularly to such a control system which provides for high resolution color display to the individual picture element or pixel level.
2. Description of the Prior Art
Initial digital graphic displays were of the vector scan type which did not readily handle alphanumeric displays. Thus, today's graphic displays are of the raster scan type wherein display images are stored in a ROM or RAM and the address generation thereof is automatically controlled by timing circuits including vertical synchronization and horizontal synchronization and the only information needed to be supplied are sequences of ROM or RAM addresses indicating which picture elements are to be illuminated on the display. For alphanumeric character display, character generation circuits have been developed which store individual bit patterns of particular characters which are automatically fetched in proper order when the display of such individual characters is required. By storing the dot pattern of a limited number of characters in a look-up table and by storing character codes, which are to be used as indices in such a look-up table, only a limited amount of storage is required to represent a display image. A similar scheme can be used for the display of graphs, when a limited number of characters are stored from which a graph can be constructed.
Display systems have been designed which provide greater resolution and clarity of characters by displaying images of those characters which were made up of a plurality of different gray-scale levels or levels of luminance such as disclosed in the Seitz et al. U.S. Pat. No. 4,158,200. However, these systems use more storage for the look-up table, in which the characters are stored, as they read more than one bit per dot to represent the gray-scale levels. This was impractical in the past because of the large amount of storage required to store the given number of bits for each pixel. However, great improvements have been made in increasing storage densities of integrated circuit random access memories from 1K RAMS to 4K RAMS, to 16K and 64K RAMS and 256K RAMS will soon be on the market. This allows the display memory to store a sufficient number of information bits to utilize every pixel on the display screen for both alphanumeric and graphic display. A particular graphic display controller which is commercially available is marketed by NEC Electronics, U.S.A., Inc. and described in a functional specification for their .mu.PD 7220/GDC Specification.
High resolution graphic images are displayed out of a large store containing a number of bits to define each dot or pixel on the display screen. Such a store is referred to as a bit map store, as there is a one-to-one correspondence, or mapping between each pixel on the screen and one or more bits in the store. One bit must be used to describe each pixel in a monochrome, non gray-level graphic display. The contents of the bit map store can be updated from a main store which is part of the host processor driving the graphic display controller.
A typical display system uses about 480 scan lines, each containing 640 picture elements or pixels. Thus for each screen image 480.times.640 or 307,200 pixels need to be stored. A commercially available graphic display controller such as described above can address up to 64 64K dynamic RAM chips or slightly over four million bits. This allows for 13.6 screen images to be stored for the above 480 by 640 configuration. During image display, 16 bit segments are read out of the bit map store and supplied serially to the display monitor.
With the above described system, one bit of storage per pixel is adequate for two-state representations of a graphic image such as black and white. However, if a gray-scale or color image is desired, then more information bits are required per pixel, i.e., two bits for four levels or colors, three bits for eight levels or colors, and so forth. The amount of storage described above is sufficient to use for a multi-level or color display image store, while a single controller can be used to generate the images. However, in that case that graphic display controller will spend more time to generate the images as more than one bit per pixel needs to be generated. The bits used for each pixel are stored in logically separate storage areas, one for each pixel bit, called bit planes.
In the above described system, the graphics display controller (GDC) can write into multiple planes, but only into one plane at a time. The GDCs address space is divided up into several parts, each part corresponding to a plane. Each time the GDC writes a colored line, it must draw the line in each plane. This line is set or reset in a particular plane, depending on the color selected for that line. To increase the performance of a color system one GDC is used for each plane of memory. A GDC is sent its drawing commands and starts drawing. While it draws, another GDC can be set up and given a drawing command and so forth. To further increase performance, it is possible to write the same commands to all GDCs at the same time.
It is then an object of the present invention to provide an improved high resolution graphic control system for graphic display.
It is another object of the present invention to provide an improved high resolution graphic display system with a plurality of bit planes and graphic controllers under simultaneous command of a host processor.
It is still a further object of the present invention to provide an improved high resolution graphic display system that can automatically handle such tasks as filling in colors in an arbitrary boundary.